The present invention relates to a scan flip flop which is capable of high speed operation and which can be formed by a small number of transistors.
In a logic circuit of a semiconductor integrated circuit, a flip flop greatly influences the area, power consumption, and critical path delay, and therefore, reduction in the area of the flip flop, reduction in the power consumption, and higher processing speed have been demanded. A scan flip flop has been used in many devices for readily achieving a test for a designed LSI circuit. Especially, reduction in the area, reduction in the power consumption, and increase in the operation speed are significant challenges in the scan flip flop.
In recent years, a flip flop using a latch circuit which takes in data within a pulse width period shorter than a clock cycle has been proposed for high speed processing applications. Hereinafter, a conventional example of a flip flop having such a structure is described with reference to the circuit diagrams of FIGS. 11 and 12.
FIG. 11 shows a scan flip flop called a SDFF (Semi-Dynamic Flip-Flop), which is an exemplary structure disclosed in the specification of U.S. Pat. No. 5,898,330 (hereinafter, referred to as “conventional example 1”).
In FIG. 11, “D” denotes a data signal, “CK” denotes a clock signal, “SI” denotes a test input signal, “SCAN” denotes a test selection signal, “Q” denotes an output signal, “VDD” denotes a VDD power supply, and “GND” denotes a GND potential.
Reference numerals “N20” to “N23” denote nMOS transistors. The series connection of the nMOS transistors N20 and N21 and the series connection of the nMOS transistors N22 and N23 are connected in parallel to constitute a selector circuit S0. In this structure, any one of the control of the nMOS transistor N21 based on data signal D and the control of the nMOS transistor N23 based on test input signal SI is exclusively selected by the nMOS transistor N20 which is controlled by an inversion signal of test selection signal SCAN from an inverter circuit INV7 and the nMOS transistor N22 which is controlled by test selection signal SCAN.
Reference numeral “P1” denotes a pMOS transistor having a source connected to the VDD power supply, and reference numeral “N3” denotes an nMOS transistor having a source connected to the GND potential. Clock signal CK is input to the gate of the pMOS transistor P1 and the gate of the nMOS transistor N3. An nMOS transistor N1 is connected in series to the drain of the pMOS transistor P1. The selector circuit S0 is inserted in series between the source of the nMOS transistor N1 and the drain of the nMOS transistor N3. The drain of the pMOS transistor P1 and the drain of the nMOS transistor N1 are connected at a connection node X1. The output terminal of a 2-input NAND circuit ND1 is connected to the gate of the nMOS transistor N1. One of the input terminals of the NAND circuit ND1 is connected to the connection node X1, and the other input terminal of the NAND circuit ND1 receives clock signal CK delayed by two inverter circuits INV1 and INV2. The inverter circuit INV2 and one input terminal of the NAND circuit ND1 are connected at a connection node CKD.
The node X1 is connected to the gate of a pMOS transistor P2 and the gate of an nMOS transistor N5. The source of the pMOS transistor P2 is connected to the VDD power supply. The source of the nMOS transistor N5 is connected to the GND potential. An nMOS transistor N4 is connected in series between the pMOS transistor P2 and the nMOS transistor N5. The gate of the nMOS transistor N4 receives clock signal CK. Herein, the output potential obtained from the connection node of the pMOS transistor P2 and the nMOS transistor N4 is output signal Q.
A latch circuit formed by inverter circuits INV3 and INV4 is connected to the node X1. A latch circuit formed by inverter circuits INV5 and INV6 is connected to the drain of a pMOS transistor which outputs output signal Q.
Next, an operation of the scan flip flop having the above structure is described.
In the first place, the operation carried out when test selection signal SCAN is at the low level, i.e., when data signal D is selected, is described.
In a period when clock signal CK is at the low level, the pMOS transistor P1 is turned on so that the potential of the node X1 rises to the high level. In this case, the nMOS transistor N4 and the pMOS transistor P2 are cut off, and therefore, output signal Q is retained unchanged at the previous value.
Then, when clock signal CK transitions to the high level, the potential of the node CKD does not immediately transition to the high level. The transition of the potential of the node CKD to the high level is delayed by the inverter circuits INV1 and INV2. During the time when clock signal CK is at the high level and the potential of the node CKD is at the low level (hereinafter, referred to as “evaluation period”), the nMOS transistor N1 is in the on state. If data signal D is at the high level during this period, the node X1 transitions from the high level to the low level, and output signal Q is raised to the high level by the pMOS transistor P2. If data signal D is at the low level during the evaluation period, the node X1 remains at the high level, and output signal Q is lowered to the low level by the nMOS transistors N4 and N5.
Then, the state where clock signal CK is at the high level and the potential of the node CKD is at the high level (hereinafter, referred to as “retainment period”) is entered. If the potential of the node X1 is at the high level at this timing, the nMOS transistor N1 is cut off by the 2-input NAND circuit ND1. Thus, the high level potential is retained by the inverter circuits INV3 and INV4 without being influenced by the value of data signal D. In the case where the node X1 is at the low level and the retainment period is entered, the pMOS transistor P1 is cut off. Therefore, the potential of the node X1 is retained at the low level by the inverter circuits INV3 and INV4 irrespective of the value of data signal D.
In general, an inverter circuit is formed by 2 MOS transistors, and a 2-input NAND circuit is formed by 4 MOS transistors. Thus, the flip flop circuit of conventional example 1 shown in FIG. 11 is formed by 28 MOS transistors in total.
FIG. 12 shows another structure example of a scan flip flop circuit called a SDFF (hereinafter, referred to as “conventional example 2”). It should be noted that like elements are denoted by like reference numerals used in FIG. 11, and the descriptions thereof are herein omitted.
The scan flip flop of FIG. 12 has the same function as that of the scan flip flop of FIG. 11. However, the scan flip flop of FIG. 12 is different from the scan flip flop of FIG. 11 in that the nMOS transistor N1 and the NAND circuit ND1 of conventional example 1, which are provided for retaining the potential of the node X1 (corresponding to a node n1 of FIG. 12) at the high level during the retainment period, are omitted and an AND/OR inverter circuit AOI1 and an AND/OR inverter circuit AOI2 are added instead. The AND/OR inverter circuit AOI1 is formed by a 2-input AND circuit and an OR inverter circuit to which the output of the 2-input AND circuit and test selection signal SCAN are input. The AND/OR inverter circuit AOI2 is formed by a 2-input AND circuit and an OR inverter circuit to which the output of the 2-input AND circuit and an inversion signal of test selection signal SCAN from the inverter circuit INV7 are input. With this structure, when clock signal CK rises from the low level to the high level while data signal D is at the low level, the potential of the node CKD transitions from the low level to the high level during the retainment period. Therefore, the nMOS transistors N20 and N22 are cut off irrespective of the value of test selection signal SCAN. Thus, the structure of FIG. 12 also achieves the function of retaining the potential of the node X1 at the high level irrespective of the value of data signal D as achieved with the nMOS transistor N1 of FIG. 11.
In general, an AND/OR inverter circuit is formed by 6 MOS transistors. Thus, the circuit shown in FIG. 12 is formed by 35 MOS transistors in total.
However, in the conventional scan flip flop of FIG. 11, the number of transistors which operate based on data signal D between the node X1 and the ground is 4, i.e., there are four nMOS transistors N1, N20, N21 and N3 serially connected between the node X1 and the ground. This structure causes a long delay time in a transition of the potential of the node X1.
In the conventional flip flop of FIG. 12, one of the serially-connected transistors is removed for reducing the delay time. However, the total number of transistors is increased because of the AND/OR inverter circuits AOI1 and AOI2 which are added for maintaining the same function. As a result, the number of MOS transistors used in the entire flip flop is increased.